With CoWoS Fully Booked, Will AI Compute Change Lanes?

If the most advanced wafer fab can produce chips but can't assemble several chips into a working AI accelerator, whose bottleneck is it really? Seeing that TSMC's CoWoS capacity allocation for next year is fully booked and some customers are shifting to Intel's EMIB-T, my first reaction wasn't "Intel is back," but rather "packaging has finally stepped into the spotlight."

Let me explain a few terms first. CoWoS is TSMC's advanced packaging, placing the main chip and High Bandwidth Memory (HBM) on the same substrate, connected via a silicon interposer. EMIB-T is Intel's Embedded Multi-die Interconnect Bridge; instead of laying a large interposer, it places bridges between chips to stitch multiple dies together. Fabless refers to chip design companies without their own wafer fabs.

Short term: Whoever ships on time earns a seat at the table

In labs, compute is often understood as card count. Since joining, I've been using K8s (container orchestration system) clusters to schedule tasks, and the more I run, the more I feel card count is just superficial. What truly determines if things can run is the entire chain: wafers, HBM (High Bandwidth Memory), packaging, substrates, and testing. CoWoS being fully booked shows the bottleneck isn't whether the wafer fab has machines, but whether the back-end can package chips into usable products.

Short term, time is the most realistic factor. Reports mention that TSMC's large-area solutions, like 14-reticle CoWoS and panel-level CoPoS, won't be ready until after 2028 at the earliest. Google's next-gen TPU is also stuck in 2027/2028. For design firms, no matter how elegant the roadmap, missing the product window is a fatal flaw. Shifting to EMIB-T isn't sudden worship of Intel, but finding a path to mass production on time.

Yield and cost are key variables. Foreign media say EMIB-T back-end yield exceeds 90%, mass production is expected next year, and estimated cost is about half of CoWoS. I dare not treat these numbers as definitive conclusions; metrics, sizes, and test flows can skew results. But the direction is clear: If packaging can compress costs while meeting scenarios like inference ASICs (Application-Specific Integrated Circuits) and cloud acceleration cards that don't require maximum bandwidth, it can absorb overflow orders.

TSMC won't sit still either. Late July reports say it's developing quasi-EMIB, similar to EMIB, aiming to simplify steps, shorten cycles, and reduce costs. This actually proves competition isn't about who is more advanced, but who can turn packaging into replicable capacity. Short term, order overflow looks more like a capacity scheduling issue than technological substitution.

Long term: Packaging shifts from back-end process to platform competition

Previously, packaging was like the wrapping done after the chip was finished. Not anymore. AI accelerators are increasingly becoming assemblies of compute chiplets, memory chiplets, and IO chiplets. How they are stitched together determines bandwidth, power consumption, area, cost, and whether the software ecosystem remains stable. Advanced packaging thus transforms from a manufacturing step into a platform capability.

This is why EMIB-T is getting attention. It's not just a backup plan; it could become another route. If customers can choose packaging, bargaining power and flexibility increase. TSMC CEO C.C. Wei also said he hopes related technologies have promising prospects to share capacity pressure and give customers greater flexibility. Sounds polite, but it's blunt: The capacity advantage of a monopoly is starting to be diluted by multi-solution competition.

However, don't understand competition as replacement. ASE Holdings COO Wu Tianyu meant roughly the same thing: CoWoS, EMIB, and other packagings are not mutually exclusive. High-end training chips will likely still need the widest interconnects and strongest memory integration; mid-range inference, network switching, and some cloud ASICs might prefer lower-cost, smoother-delivery bridging solutions. Packaging will stratify, and so will customers.

Long term, there's another trend: Ecosystem boundaries are loosening. Reports mention that the advanced packaging ecosystem, originally monopolized by TSMC for front-end and back-end, is being forced open due to exploding AI demand, with billions of dollars in advanced packaging products involving cross-fab collaboration. In the future, chip design might not mean choosing one foundry, but calculating accounts separately for front-end, packaging, testing, and substrates.

For people in AI Labs, the impact is real. Short term, training cards might remain expensive because packaging bottlenecks won't disappear overnight, and HBM and substrates are also tight. Long term, if multiple packaging solutions mature, inference chip costs have a chance to drop. Especially for us, who just used qwen3.8-max for experiments and use K8s for scheduling, what we truly care about is whether the same budget can run more services.

So the most noteworthy aspect of this news isn't whether CoWoS is fully booked, but that advanced packaging is starting, for the first time, to schedule capacity by quarter and lock allocations by customer, just like wafer fabs. Chip companies compete not just on transistors, but on who can stitch a bunch of chiplets into a working machine on time next year. Looking forward, if packaging continues to steal the show, the price curve for AI compute might come down later than we think.