From baseband power tuning to AI for Science: Chip engineer on Seed STEM Scientist Plan challenges

Last week, while debugging a 5G NR baseband IP on a 7nm process, I ran into a classic "power wall" issue: at peak data rates, the dynamic power consumption of the RF front-end was 12% higher than expected, pushing the junction temperature close to its reliability limit. The standard approach is to run dozens of SPICE simulation rounds, tweaking transistor sizes a few at a time and observing how waveforms affect power. But this round of simulations took three days to complete—because the parasitic parameter extraction for the entire PA chain used full-chip-level RC.